These are some notes and projects on working with FPGAs.
A roundup of current entry-level FPGA boards, updated March 2011.
J1 is a minimal 16-bit stack-based CPU that can run Forth at 100 MIPS. Designed for FPGAs and coded in under 200 lines of Verilog, it uses block RAM for code and data, has large internal stacks, and executes one instruction per cycle without pipelining.
A tiny stack-based 16-bit CPU from 2003.
Python loader for the popular XESS XSA-3S1000 development board.
You can make an incredibly compact FIFO from Xilinx SRL16E primitives.
Signed operations and values have been part of Verilog for about a decade. This article explains a few common uses of signed values, and shows how to mix operations involving signed and unsigned values.
Notes on how to derive a fractional lower frequency clock in VHDL and Verilog.
A minimal Makefile for building Xilinx WebPack ISE projects on Linux/Unix.
fpga4fun - FPGA projects and tutorials
John’s FPGA Page - VHDL and FPGA resources, many CPU projectsMail: email@example.com